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Macros</h2></td></tr>
<tr class="memitem:ga2b30ef24c0847197fa8ac1bc4aff814c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tpg__v3__0.html#ga2b30ef24c0847197fa8ac1bc4aff814c">XTpg_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__tpg__v3__0.html#ga7819ce0a2967c5280608b10aa1105c4b">XTpg_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="separator:ga2b30ef24c0847197fa8ac1bc4aff814c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad294faacba4217a983999dfe77420cce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tpg__v3__0.html#gad294faacba4217a983999dfe77420cce">XTpg_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__tpg__v3__0.html#ga91dbe9f1b10ad6b35befc74c7dde4b28">XTpg_Out32</a>((BaseAddress) + (u32)(RegOffset), (Data))</td></tr>
<tr class="separator:gad294faacba4217a983999dfe77420cce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">TPG registers offsets</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Control register bit masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt register bit masks. It is applicable for</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Status and IRQ_ENABLE Registers </p>
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<tr><td colspan="2"><div class="groupHeader">Error register bit mask definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Version register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Active Size register bit masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Pattern Control register bit masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Pattern values of Pattern Control register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Motion Speed register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Cross Hair register bit masks and shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">ZPlate Horizontal Control register bit masks and shift</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">ZPlate Vertical Control register bit masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Box Size register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">TPG Box Color register bit masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Stuck Pixel Threshold register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Noise Gain register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Bayer Phase register bit mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">General purpose masks</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Backward compatibility macros</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Enable and Status Registers Offsets</div></td></tr>
<tr class="memitem:gad6b8d7c17d6e94a346011e3fd3ed7b42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__tpg__v3__0.html#gad6b8d7c17d6e94a346011e3fd3ed7b42">XTPG_ISR_OFFSET</a>&#160;&#160;&#160;<a class="el" href="group__tpg__v3__0.html#gaac60a6adc8b96f9410f851500fbc2123">XTPG_STATUS_OFFSET</a></td></tr>
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